Parallel- in, Parallel- out, Universal Shift Register. A universal shift register is a do- everything device in addition to the parallel- in/ parallel- out function.

The operation of SIPO is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel data output. If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned LOW again to logic “0” giving us one data pulse or 0-1-0. The second clock pulse will change the output of FFA to logic “0” and the output of FFB and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic “1” has now moved or been “shifted” one place along the register to the right as it is now at QA.

When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level “0” because the input to FFA has remained constant at logic level “0”. The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the register. This data value can now be read directly from the outputs of QA to QD. Then the data has been converted from a serial data input signal to a parallel data output. The truth table and following waveforms show the propagation of the logic “1” through the register from left to right as follows.

In Serial In Parallel Out (SIPO) shift registers, the data is stored into the register serially while it is retrieved from it in parallel-fashion. Figure 1 shows an n-bit synchronous SIPO shift register sensitive to positive edge of the clock pulse. Here the data word which is to be stored (Data in) is fed serially at the input of the first (D 1 of FF 1). It is also seen that the inputs of all other flip-flops (except the first flip-flop FF 1) are driven by the outputs of the preceding ones say for example, the input of FF 2 is driven by the output of FF 1. In this kind of, the data stored within the register is obtained as a parallel-output data word (Data out) at the individual output pins of the flip-flops (Q 1 to Q n). In general, the register contents are cleared by applying high on the clear pins of all the flip-flops at the initial stage.

After this, the first bit, B 1 of the input data word is fed at the D 1 pin of FF 1. Related pages This bit (B 1) will enter into FF 1, get stored and thereby appears at its output Q 1 on the appearance of first leading edge of the clock. Further at the second clock tick, the bit B 1 right-shifts and gets stored into FF 2 while appearing at its output pin Q 2 while a new bit, B 2 enters into FF 1. Similarly at each clock tick the data within the register moves towards right by a single bit while a new bit of the input word enters into the register. Meanwhile one can extract the bits stored within the register in parallel-fashion at the individual flip-flop outputs. Analyzing on the same grounds, one can note that the n-bit input data word is obtained as an n-bit output data word from the shift register at the rising edge of the n th clock pulse. This working of the shift-register can be summarized as in Table I and the corresponding wave forms are given by Figure 2.

Anthropology study material by examrace. In the right-shift SIPO shift-register, data bits shift from left to right for each clock tick. However if the data bits are made to shift from right to left in the same design, one gets a left-shift SIPO shift-register as shown by Figure 3. Nevertheless the basic working principle remains the same except the fact that now B n down to B 1 is stored in Q n down to Q 1 i.e. Q 1 = B 1, Q 2 = B 2 Q n = B n at the n th clock tick.